ESD protection devices need to shunt current during ESD circumstances, but need to appear like an open during normal chip operation. This is achieved through the so-called trigger elements, a.k.a. ESD detectors. The trigger element needs to fulfill many requirements such as it must never trigger below the supply voltage (+margin) to prevent latch-up (if no transients); it must not trigger on transients caused by switching, noise, current injection or any other event during the normal operation of the chip; it must trigger before the failure voltage (−margin) of the devices it needs to protect and the leakage at the supply voltage needs to be within certain predefined limits. In many ESD applications a design window of an ESD protection circuit is so small that finding a trigger element which fits within this window fulfilling the above discussed requirements is very difficult.
One of the ESD protection circuits includes voltage level detection devices or circuits that need to be biased at a certain voltage level (trigger voltage) in order to conduct. These can be further divided into snapback devices (devices that go to a low-ohmic state with a voltage offset lower than the trigger voltage) and non-snapback devices that go to a low-ohmic state with a voltage offset equal to the trigger voltage. However, many of such voltage level detection devices trigger at a too high voltage and others have a too high leakage. An example of this is an ESD protection of an output driver . . . . The output NMOS transistor can be quickly turned. So, in the worst case the NMOS will trigger at its holding voltage. This means it is impossible to use a gate-grounded NMOS (ggNMOS) or any device that uses a ggNMOS as trigger element to protect such an output unless the failure voltage of the output driver is greater than the trigger voltage of the ggNMOS. In the case where the supply voltage is low enough, a diode chain (or any device that uses a diode chain as trigger element) could be used as ESD protection. However, this is limited by leakage considerations. The voltage drop over each diode should be sufficiently small so that hardly any leakage current flows through it. For higher supply voltages this can become a problem.
The solution to the above problem is generally solved by another type of ESD protection circuit that includes a transient detection circuit that only conducts when the voltage changes with time fast enough and can trigger at a low voltage level. An example of such a transient circuit is a form of RC controlled MOS device (or any device triggered by it). As long as a MOS operates in MOS-mode (if the current density stays below about 0.5 mA/um for an NMOS) the voltage over the MOS will be below its holding voltage. Therefore, it can be used to protect a device that can fails below the holding voltage of the ESD clamp (or at Vt2<Vt1). Despite the overall effectiveness of this approach there are some downsides and limitations. First, this approach consumes a lot of area. The RC chain is usually very large, and the MOS itself has to be large enough to be able to conduct enough current in MOS mode (either all ESD current or just the (possibly high) trigger current of another device). Another downside is that the time constant is influenced by parasitic capacitances along the chip. These may slow down the pulse and delay triggering, increasing the trigger voltage as well. Also noise or spikes on the powerline will induce an extra leakage path. Finally, when using RC controlled MOS devices as a trigger element of another device (e.g. an SCR), and when too many clamps are placed in parallel, it is possible that trigger current will become very high. This generally does not cause any problems for core protection, as the voltage over the parallel clamps will never exceed the maximum voltage over a single clamp, but it can create a problem for IO protection, where typically dual diodes are used as protection. All ESD current when stressing the IO has to go through one of these diodes. If the current demand of the parallel trigger elements is too high the total voltage over the sensitive node may become too high. This is the combined result of all current going through the diode's resistance and not enough of the current running through each individual clamp circuit preventing the clamps from triggering. Thus, several deficiencies with this transient detection circuit are that it has larger area and includes latch-up risk and further only one clamp can trigger at a low voltage because the transient dissipates after triggering.
Thus, there is a need in the art to provide a protection technique for ESD protection that overcomes the disadvantages of the above discussed prior art by providing a voltage level detection trigger device such that the trigger voltage can be easily altered to a desired value while maintaining a low leakage current.